Objective type question and answers for VLSI Design, also supports Electronics Devices and Circuits to some extent.
VLSI Design (Objective Type) Download
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UNIT
- 1
Multiple choice
1.
The speed – power product of any MOS technology is measured in [ C ]
a)KJ
b)
MW-sec c) PJ d)
Joules
2.
For depletion mode mosfet,
threshold voltage [ D ]
a) 0.2 V DD b)
-0.2 V DD c)
0.8 V DD d) -0.8 V DD
3.
The technology which is characterized by high speed [ D ]
a)CMOS
b) BICMOS
c) GaAs
d)ECL
4.
Latch up in cmos device can be
avoided by [ B ]
A) Increasing temp b) doping control c) increasing the substrate resistance
d)decreasing
substrate doping level
5.
Material used for metallization is
[ A ]
a)Aluminum b)
copper c)silver d)tungsten
6. Material used for gate oxide in MOS
technology. [ C ]
a) Si b)
Ge c) Sio2 d)
AlO2
7.
Poly silicon is a _________ material [ C ]
a) Crystalline b) Amorphous c) Poly crystalline d) None
8.
Silicide is combination of [ A ]
a) Metal
–poly b) Metal-Silicon c) Metal-Ge d) Metal-SiO2
9.
In modern CMOS fabrication, the pattern on each layer is created by
a) Ion implantation b) Oxidation c) Photo lithography d) Encapsulation
10.
The advantage of twin- tub process [
C ]
a) Low complexity b) Low cost depletion c) Latch up immunity d) high mask count
Fill in the
blanks:
11.
Expansion of CVD is chemical vapour
deposition
12.
Electron lithography is
preferred in submicron device dimension
13.
The kinetics of thermal oxidation is modeled deal and groover model.
14.
The static power dissipation in CMOS technology is zero
15.
In normal mode of operation in CMOS, substrate terminal of NMOS is connected to
Vss and substrate
terminal of PMOS is connected to Vdd
16. CMOS technology is high delay than bipolar Technology
17.
The deficiency of mos technology
is limited load driving capacity
18.
Under DEPLETION mode NMOS is ON
state.
19.
NMOS FET’s are faster than
PMOS FET’s
20.
Power dissipation in NMOS technology is high
compared to CMOS technology.
UNIT - 2
Multiple choice
1. MOSFET operated in saturation when
[ C ]
(a)
Vds = vgs-vt (b) vds < vgs-vt
(c) Vds > vgs-vt (d) Vds < vt
2.
For faster NMOS circuits, one would
choose the following type of substrate [ B ]
(a) 110 Oriented n - type substrate (c) 111 Oriented p -
type substrate
(b) 100 oriented p - type substrate (d) 111 oriented n-
type substrate
3.
Pull up to pull down ratio for n MOS inverter driven by another n MOS inverter
is [ D ]
(a)
4:4 (b) 4:1 (c)
1:4 (d)
8:1
4.
The following device is less likely to suffer latch up [ C ]
(a)n
MOS (b)
CMOS (c) BICMOS (d) PMOS
5.
In cmos inverter if βn=βp & if Vtn =Vtp, then the logic levels are
disposed about at a point where [ C ]
(a)VIN
= Vout = 0.1 VIN
(b VIN = 0.5 VDD (c)
VIN = Vout =0.5 VDD (d) VIN = Vout = VDD
6.
The figure of merit of MOS transistor can be expressed as [ C ]
7.
Typical mobility of holes (Bulk) is [ D ]
a) 650cm2/V.sec b) 240 cm2/V.sec c) 1250 cm2/V.sec d)
480 cm2/V.sec
8.
Pickup the ‘true’ statement with respect to Bi-CMOS Inverter [ C ]
a) Low input impedance b) High output impedance c)
high noise margin
d) Low driving capability
9.
To achieve best performance NMOS inverter transfer characteristics, Zpu/Zpd
ratio should be
a) Zero b) One c) As low as possible d) As high as possible [ C ]
10.
Number of transistors to implement three-input AND gate using pass transistor
logic is
a) 6 b) 3 c)
5 d) 9 [ B ]
Fill in the
blanks:
11.
An inverter driven through one or more pass transistor should have Zpu/Zpd
ratio of 8:1
12.
The threshold voltage is increased due to body
effect
13.
More lightly doped substrate less will
be the body effect
14. The
drain- source current (IDS) for NMOS under saturation can be
expressed as
15.
Transconductance of MOS transistor (gm) is expressed as
16.
For devices of similar dimension n-channel is faster than the p – channel
17.
A simple bicmos inverter has high input impedance and low output impedance
18.
The power dissipation is low in CMOS
technology.
19.
Bi-CMOS inverter has high driving capability than cmos technology .
20.
For high performance CMOS inverter 
should be low.
UNIT – 3
Multiple choices
1.
The color encoding for polysilicon is [ A ]
(a) Red (b) Green
(c) Blue (d) Orange
2.
The color encoding of ‘VIA’ in double metal CMOS p-well process [ B ]
(a) Red b) Black c) Brown d) Yellow
3.
Metal 1 to metal 1 spacing in layout design is [ C ]
(a) 4
λ (b) 2λ (c)3λ (
d) 1λ
4. The buried contact is made
between [ B ]
(a)
Poly to metal (b) poly to diff (c) poly
to diff using metal (d) Metal to metal
5.In NMOS layout design
style, the colour of contact cut [ A ]
a) Black b) Green c) Blue d) Red
6.
What is color of metal 1 (CMOS encoding) [ B ]
a) Black b) Blue c) Red d) Yellow
7.
The p-type transistors are placed above the [ C ]
a) Poly silicon b) diffusion c) Demarcation line d)
metal
8.
The minimum gap between diffusion and diffusion is [ A ]
a) 2 λ b) 5 λ c) 7 λ d) 10 λ
9.
The size of a transistor is usually designed in terms of [
D ]
a) Drain b) source c)
metal d) channel length
10.
According to 2µm CMOS technology, the minimum separation between contact cuts
a) 2 µm b) 4
µm c) 6 µm d) 5 µm [ B ]
Fill in the
blanks
11.
The layer preferred for global distribution of power buses is METAL 2
12.
STICK DIAGRAM is used to
convey layer information.
13.
For cmos circuits stick encodings
for demarcation line is BROWN
in color.
14.
The power and ground lines often called POWER
RANGE
15.
The minimum width of metal 1 layer is 3λ
16.
A MOS TRANSISTOR is formed
wherever polysilicon crosses Diffusion
17.
Metal 1 for LOCAL DISTRIBUTION
and metal 2 for GLOBAL DISTRIBUTION
of power lines in stick notation
18.
The minimum polysilicon width is 2λ.
19.
As fabrication technology improves, the heat sink size REDUCES.
20. In CMOS design style, Demarcation line is shown by DOTTED LINE
UNIT – 4
Multiple choice
1.
Power dissipation per unit area is scaled by [ C ]
2.
Typical value of Diffusion capacitor(C area ) in 5 µm technology [ A ]
a) 1.0x10 – 4 pF/µm2 b) 1.0X10 – 2 pF/µm2= c) 0.1x10 – 4 pF/µm2 d) 0.1x10 – 2 pF/µm2
3.
The rise time of CMOS inverters is [ C ]
4. The typical value of load
capacitance is [ D ]
a)
CL
< 10 4 cg (b) CL 
10 4 cg (c) CL
= 10 14 cg (d) CL 10 14 cg
5. The characteristics of a metal
layer are
[ A
]
a) Low R; low C b) low R; moderate C c) Low R; moderate C d)
moderate R; high C
6. The typical sheet resistance of
polysilicon for 5µm is [ D ]
a)
0-10
Ω b) 10-14 Ω c) 120 to 140Ω d)
15 to 100 Ω
7.
The overall delay Td for n sections is given by [ B ]
a) Td= nrc (
) b) Td=
n2 rc() c) Td
= n2r2 c() d) Td= n r2 c()
8.
Deposition of the metal/silicon alloy prior to sintering may be done with [ A ]
a)
Sputtering b) diffusion c) Implantation d) Metallization
9.
What is the formula for Rise-time estimation [ A ]
a) Tr=
b) Tr = 
c) Tr
= 
d) Tr = 
10.
The formula for fall-time estimation in CMOS inverter is [ C ]
a)
Tf = 
b) Tf = 
c) Tf =
d) 
Fill in the blanks
11. The propagation delay of n
sections is given by
12. The layer in which metal is deposited
on poly silicon is called SILICIDE.
13. The sheet resistance of p–diff
is 2 : 5 times that of n-diffusion.
14. The values for N-diffusion
region are 0.4 times
the P-diffusion regions.
15. Bi-CMOS technology is reasonably
good for HIGH LOW DRIVING CAPABILITY
16. Power consumption in CMOS
circuits depends on FREQUENCY
at which they operate.
17. METAL 1 layer is
suitable for routing Vdd or Vss.
18. The LARGE CAPACITIVE load can’t be driven by a single inverter.
19. In Bi-Polar transistor collector
current depends EXPONENTIALY on
Vbe.
20. The Delay for Bi-CMOS inverter
is REDUCED by a factor of h f
e
compared with a CMOS Inverter.
